processor.h File Reference

#include <gctypes.h>
#include "asm.h"

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Macros
#define	__stringify(rn)   #rn
#define	ATTRIBUTE_ALIGN(v)   __attribute__((aligned(v)))
#define	STACK_ALIGN(type, name, cnt, alignment)
#define	_sync()   asm volatile("sync")
#define	_nop()   asm volatile("nop")
#define	ppcsync()   asm volatile("sc")
#define	ppchalt()
#define	mfpvr()
#define	mfdcr(_rn)
#define	mtdcr(rn, val)   asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
#define	mfmsr()
#define	mtmsr(val)   asm volatile("mtmsr %0" : : "r" (val))
#define	mfdec()
#define	mtdec(_val)   asm volatile("mtdec %0" : : "r" (_val))
#define	mfspr(_rn)
#define	mtspr(_rn, _val)   asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
#define	mfwpar()   mfspr(WPAR)
#define	mtwpar(_val)   mtspr(WPAR,_val)
#define	mfmmcr0()   mfspr(MMCR0)
#define	mtmmcr0(_val)   mtspr(MMCR0,_val)
#define	mfmmcr1()   mfspr(MMCR1)
#define	mtmmcr1(_val)   mtspr(MMCR1,_val)
#define	mfpmc1()   mfspr(PMC1)
#define	mtpmc1(_val)   mtspr(PMC1,_val)
#define	mfpmc2()   mfspr(PMC2)
#define	mtpmc2(_val)   mtspr(PMC2,_val)
#define	mfpmc3()   mfspr(PMC3)
#define	mtpmc3(_val)   mtspr(PMC3,_val)
#define	mfpmc4()   mfspr(PMC4)
#define	mtpmc4(_val)   mtspr(PMC4,_val)
#define	mfhid0()   mfspr(HID0)
#define	mthid0(_val)   mtspr(HID0,_val)
#define	mfhid1()   mfspr(HID1)
#define	mthid1(_val)   mtspr(HID1,_val)
#define	mfhid2()   mfspr(HID2)
#define	mthid2(_val)   mtspr(HID2,_val)
#define	mfhid4()   mfspr(HID4)
#define	mthid4(_val)   mtspr(HID4,_val)
#define	__lhbrx(base, index)
#define	__lwbrx(base, index)
#define	__sthbrx(base, index, value)   __asm__ volatile ("sthbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
#define	__stwbrx(base, index, value)   __asm__ volatile ("stwbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
#define	cntlzw(_val)
#define	_CPU_MSR_GET(_msr_value)
#define	_CPU_MSR_SET(_msr_value)   { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
#define	_CPU_ISR_Enable()
#define	_CPU_ISR_Disable(_isr_cookie)
#define	_CPU_ISR_Restore(_isr_cookie)
#define	_CPU_ISR_Flash(_isr_cookie)
#define	_CPU_FPR_Enable()
#define	_CPU_FPR_Disable()

Functions
static u16	bswap16 (u16 val)
static u32	bswap32 (u32 val)
static u64	bswap64 (u64 val)
static u32	read32 (u32 addr)
static void	write32 (u32 addr, u32 x)
static void	mask32 (u32 addr, u32 clear, u32 set)
static u16	read16 (u32 addr)
static void	write16 (u32 addr, u16 x)
static u8	read8 (u32 addr)
static void	write8 (u32 addr, u8 x)
static void	writef32 (u32 addr, f32 x)

Macro Definition Documentation

__lhbrx

#define __lhbrx	(		base,
			index
	)

Value:

({  register u16 res;               \
    __asm__ volatile ("lhbrx    %0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
    res; })

__lwbrx

#define __lwbrx	(		base,
			index
	)

Value:

({  register u32 res;               \
    __asm__ volatile ("lwbrx    %0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
    res; })

__sthbrx

#define __sthbrx	(		base,
			index,
			value
	)		__asm__ volatile ("sthbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")

__stringify

#define __stringify

(

rn

)

#rn

__stwbrx

#define __stwbrx	(		base,
			index,
			value
	)		__asm__ volatile ("stwbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")

_CPU_FPR_Disable

#define _CPU_FPR_Disable

(

)

Value:

{ register u32 _val = 0; \
      asm volatile ("mfmsr %0; rlwinm %0,%0,0,19,17; mtmsr %0" : \
                    "=&r" (_val) : "0" (_val));\
}

_CPU_FPR_Enable

#define _CPU_FPR_Enable

(

)

Value:

{ register u32 _val = 0; \
      asm volatile ("mfmsr %0; ori %0,%0,0x2000; mtmsr %0" : \
                    "=&r" (_val) : "0" (_val));\
}

_CPU_ISR_Disable

#define _CPU_ISR_Disable

(

_isr_cookie

)

Value:

{ register u32 _disable_mask = 0; \
    _isr_cookie = 0; \
    __asm__ __volatile__ ( \
      "mfmsr %0\n" \
      "rlwinm %1,%0,0,17,15\n" \
      "mtmsr %1\n" \
      "extrwi %0,%0,1,16" \
      : "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) \
      : "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    ); \
  }

_CPU_ISR_Enable

#define _CPU_ISR_Enable

(

)

Value:

{ register u32 _val = 0; \
      __asm__ __volatile__ ( \
        "mfmsr %0\n" \
        "ori %0,%0,0x8000\n" \
        "mtmsr %0" \
        : "=&r" ((_val)) : "0" ((_val)) \
      ); \
    }

_CPU_ISR_Flash

#define _CPU_ISR_Flash

(

_isr_cookie

)

Value:

{ register u32 _flash_mask = 0; \
    __asm__ __volatile__ ( \
    "   cmpwi %0,0\n" \
    "   beq 1f\n" \
    "   mfmsr %1\n" \
    "   ori %1,%1,0x8000\n" \
    "   mtmsr %1\n" \
    "   rlwinm %1,%1,0,17,15\n" \
    "   mtmsr %1\n" \
    "1:" \
    : "=r" ((_isr_cookie)), "=&r" ((_flash_mask)) \
    : "0" ((_isr_cookie)), "1" ((_flash_mask)) \
    ); \
  }

_CPU_ISR_Restore

#define _CPU_ISR_Restore

(

_isr_cookie

)

Value:

{ register u32 _enable_mask = 0; \
    __asm__ __volatile__ ( \
    "    cmpwi %0,0\n" \
    "    beq 1f\n" \
    "    mfmsr %1\n" \
    "    ori %1,%1,0x8000\n" \
    "    mtmsr %1\n" \
    "1:" \
    : "=r"((_isr_cookie)),"=&r" ((_enable_mask)) \
    : "0"((_isr_cookie)),"1" ((_enable_mask)) \
    ); \
  }

_CPU_MSR_GET

#define _CPU_MSR_GET

(

_msr_value

)

Value:

do { \
    _msr_value = 0; \
    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
  } while (0)

_CPU_MSR_SET

#define _CPU_MSR_SET

(

_msr_value

)

{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }

_nop

#define _nop

(

)

asm volatile("nop")

_sync

#define _sync

(

)

asm volatile("sync")

ATTRIBUTE_ALIGN

#define ATTRIBUTE_ALIGN

(

v

)

__attribute__((aligned(v)))

cntlzw

#define cntlzw

(

_val

)

Value:

({register u32 _rval; \
                      asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})

mfdcr

#define mfdcr

(

_rn

)

Value:

({register u32 _rval; \
        asm volatile("mfdcr %0," __stringify(_rn) \
             : "=r" (_rval)); _rval;})

mfdec

#define mfdec

(

)

Value:

({register u32 _rval; \
        asm volatile("mfdec %0" : "=r" (_rval)); _rval;})

mfhid0

#define mfhid0

(

)

mfspr(HID0)

mfhid1

#define mfhid1

(

)

mfspr(HID1)

mfhid2

#define mfhid2

(

)

mfspr(HID2)

mfhid4

#define mfhid4

(

)

mfspr(HID4)

mfmmcr0

#define mfmmcr0

(

)

mfspr(MMCR0)

mfmmcr1

#define mfmmcr1

(

)

mfspr(MMCR1)

mfmsr

#define mfmsr

(

)

Value:

({register u32 _rval; \
        asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})

mfpmc1

#define mfpmc1

(

)

mfspr(PMC1)

mfpmc2

#define mfpmc2

(

)

mfspr(PMC2)

mfpmc3

#define mfpmc3

(

)

mfspr(PMC3)

mfpmc4

#define mfpmc4

(

)

mfspr(PMC4)

mfpvr

#define mfpvr

(

)

Value:

({register u32 _rval; \
        asm volatile("mfpvr %0" : "=r"(_rval)); _rval;})

mfspr

#define mfspr

(

_rn

)

Value:

({  register u32 _rval = 0; \
    asm volatile("mfspr %0," __stringify(_rn) \
    : "=r" (_rval));\
    _rval; \
})

mfwpar

#define mfwpar

(

)

mfspr(WPAR)

mtdcr

#define mtdcr	(		rn,
			val
	)		asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))

mtdec

#define mtdec

(

_val

)

asm volatile("mtdec %0" : : "r" (_val))

mthid0

#define mthid0

(

_val

)

mtspr(HID0,_val)

mthid1

#define mthid1

(

_val

)

mtspr(HID1,_val)

mthid2

#define mthid2

(

_val

)

mtspr(HID2,_val)

mthid4

#define mthid4

(

_val

)

mtspr(HID4,_val)

mtmmcr0

#define mtmmcr0

(

_val

)

mtspr(MMCR0,_val)

mtmmcr1

#define mtmmcr1

(

_val

)

mtspr(MMCR1,_val)

mtmsr

#define mtmsr

(

val

)

asm volatile("mtmsr %0" : : "r" (val))

mtpmc1

#define mtpmc1

(

_val

)

mtspr(PMC1,_val)

mtpmc2

#define mtpmc2

(

_val

)

mtspr(PMC2,_val)

mtpmc3

#define mtpmc3

(

_val

)

mtspr(PMC3,_val)

mtpmc4

#define mtpmc4

(

_val

)

mtspr(PMC4,_val)

mtspr

#define mtspr	(		_rn,
			_val
	)		asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))

mtwpar

#define mtwpar

(

_val

)

mtspr(WPAR,_val)

ppchalt

#define ppchalt

(

)

Value:

({                  \
    asm volatile("sync");               \
    while(1) {                          \
        asm volatile("nop");            \
        asm volatile("li 3,0");         \
        asm volatile("nop");            \
    }                                   \
})

ppcsync

#define ppcsync

(

)

asm volatile("sc")

STACK_ALIGN

#define STACK_ALIGN	(		type,
			name,
			cnt,
			alignment
	)

Value:

u8 _al__##name[((sizeof(type)*(cnt)) + (alignment) + (((sizeof(type)*(cnt))%(alignment)) > 0 ? ((alignment) - ((sizeof(type)*(cnt))%(alignment))) : 0))]; \
                                                    type *name = (type*)(((u32)(_al__##name)) + ((alignment) - (((u32)(_al__##name))&((alignment)-1))))

Function Documentation

bswap16()

static u16 bswap16 ( u16  val )

inlinestatic

bswap32()

static u32 bswap32 ( u32  val )

inlinestatic

bswap64()

static u64 bswap64 ( u64  val )

inlinestatic

mask32()

static void mask32 ( u32  addr, u32  clear, u32  set  )

inlinestatic

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read16()

static u16 read16 ( u32  addr )

inlinestatic

read32()

static u32 read32 ( u32  addr )

inlinestatic

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read8()

static u8 read8 ( u32  addr )

inlinestatic

write16()

static void write16 ( u32  addr, u16  x  )

inlinestatic

write32()

static void write32 ( u32  addr, u32  x  )

inlinestatic

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write8()

static void write8 ( u32  addr, u8  x  )

inlinestatic

writef32()

static void writef32 ( u32  addr, f32  x  )

inlinestatic