#include <stdlib.h>
#include "asm.h"
#include "processor.h"
#include "spinlock.h"
#include "irq.h"
#include "exi.h"
#include "cache.h"
#include "ogcsys.h"
#include "lwp.h"
#include "lwp_threads.h"
#include "lwp_watchdog.h"
#include "lwip/debug.h"
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/pbuf.h"
#include "lwip/sys.h"
#include "netif/etharp.h"
#include "netif/gcif/gcif.h"

Include dependency graph for gcif.c:

Classes
struct	bba_descr

struct	bba_priv

struct	bba_priv::dev_stats

Macros
#define	IFNAME0 'e'

#define	IFNAME1 '0'

#define	GCIF_TX_TQ 8

#define	GCIF_EXI_TQ 9

#define	BBA_MINPKTSIZE 60

#define	BBA_CID 0x04020200

#define	BBA_CMD_IRMASKALL 0x00

#define	BBA_CMD_IRMASKNONE 0xF8

#define	BBA_NCRA 0x00 /* Network Control Register A, RW */

#define	BBA_NCRA_RESET (1<<0) /* RESET */

#define	BBA_NCRA_ST0 (1<<1) /* ST0, Start transmit command/status */

#define	BBA_NCRA_ST1 (1<<2) /* ST1, " */

#define	BBA_NCRA_SR (1<<3) /* SR, Start Receive */

#define	BBA_NCRB 0x01 /* Network Control Register B, RW */

#define	BBA_NCRB_PR (1<<0) /* PR, Promiscuous Mode */

#define	BBA_NCRB_CA (1<<1) /* CA, Capture Effect Mode */

#define	BBA_NCRB_PM (1<<2) /* PM, Pass Multicast */

#define	BBA_NCRB_PB (1<<3) /* PB, Pass Bad Frame */

#define	BBA_NCRB_AB (1<<4) /* AB, Accept Broadcast */

#define	BBA_NCRB_HBD (1<<5) /* HBD, reserved */

#define	BBA_NCRB_RXINTC0 (1<<6) /* RXINTC, Receive Interrupt Counter */

#define	BBA_NCRB_RXINTC1 (1<<7) /* " */

#define	BBA_NCRB_1_PACKET_PER_INT (0<<6) /* 0 0 */

#define	BBA_NCRB_2_PACKETS_PER_INT (1<<6) /* 0 1 */

#define	BBA_NCRB_4_PACKETS_PER_INT (2<<6) /* 1 0 */

#define	BBA_NCRB_8_PACKETS_PER_INT (3<<6) /* 1 1 */

#define	BBA_LTPS 0x04 /* Last Transmitted Packet Status, RO */

#define	BBA_LRPS 0x05 /* Last Received Packet Status, RO */

#define	BBA_IMR 0x08 /* Interrupt Mask Register, RW, 00h */

#define	BBA_IMR_FRAGIM (1<<0) /* FRAGIM, Fragment Counter Int Mask */

#define	BBA_IMR_RIM (1<<1) /* RIM, Receive Interrupt Mask */

#define	BBA_IMR_TIM (1<<2) /* TIM, Transmit Interrupt Mask */

#define	BBA_IMR_REIM (1<<3) /* REIM, Receive Error Interrupt Mask */

#define	BBA_IMR_TEIM (1<<4) /* TEIM, Transmit Error Interrupt Mask */

#define	BBA_IMR_FIFOEIM (1<<5) /* FIFOEIM, FIFO Error Interrupt Mask */

#define	BBA_IMR_BUSEIM (1<<6) /* BUSEIM, BUS Error Interrupt Mask */

#define	BBA_IMR_RBFIM (1<<7) /* RBFIM, RX Buffer Full Interrupt Mask */

#define	BBA_IR 0x09 /* Interrupt Register, RW, 00h */

#define	BBA_IR_FRAGI (1<<0) /* FRAGI, Fragment Counter Interrupt */

#define	BBA_IR_RI (1<<1) /* RI, Receive Interrupt */

#define	BBA_IR_TI (1<<2) /* TI, Transmit Interrupt */

#define	BBA_IR_REI (1<<3) /* REI, Receive Error Interrupt */

#define	BBA_IR_TEI (1<<4) /* TEI, Transmit Error Interrupt */

#define	BBA_IR_FIFOEI (1<<5) /* FIFOEI, FIFO Error Interrupt */

#define	BBA_IR_BUSEI (1<<6) /* BUSEI, BUS Error Interrupt */

#define	BBA_IR_RBFI (1<<7) /* RBFI, RX Buffer Full Interrupt */

#define	BBA_BP 0x0a/+0x0b/ /* Boundary Page Pointer Register */

#define	BBA_TLBP 0x0c/+0x0d/ /* TX Low Boundary Page Pointer Register */

#define	BBA_TWP 0x0e/+0x0f/ /* Transmit Buffer Write Page Pointer Register */

#define	BBA_TRP 0x12/+0x13/ /* Transmit Buffer Read Page Pointer Register */

#define	BBA_RWP 0x16/+0x17/ /* Receive Buffer Write Page Pointer Register */

#define	BBA_RRP 0x18/+0x19/ /* Receive Buffer Read Page Pointer Register */

#define	BBA_RHBP 0x1a/+0x1b/ /* Receive High Boundary Page Pointer Register */

#define	BBA_RXINTT 0x14/+0x15/ /* Receive Interrupt Timer Register */

#define	BBA_NAFR_PAR0 0x20 /* Physical Address Register Byte 0 */

#define	BBA_NAFR_PAR1 0x21 /* Physical Address Register Byte 1 */

#define	BBA_NAFR_PAR2 0x22 /* Physical Address Register Byte 2 */

#define	BBA_NAFR_PAR3 0x23 /* Physical Address Register Byte 3 */

#define	BBA_NAFR_PAR4 0x24 /* Physical Address Register Byte 4 */

#define	BBA_NAFR_PAR5 0x25 /* Physical Address Register Byte 5 */

#define	BBA_NWAYC 0x30 /* NWAY Configuration Register, RW, 84h */

#define	BBA_NWAYC_FD (1<<0) /* FD, Full Duplex Mode */

#define	BBA_NWAYC_PS100 (1<<1) /* PS100/10, Port Select 100/10 */

#define	BBA_NWAYC_ANE (1<<2) /* ANE, Autonegotiation Enable */

#define	BBA_NWAYC_ANS_RA (1<<3) /* ANS, Restart Autonegotiation */

#define	BBA_NWAYC_LTE (1<<7) /* LTE, Link Test Enable */

#define	BBA_HALF_100 (BBA_NWAYC_PS100)

#define	BBA_FULL_100 (BBA_NWAYC_PS100\|BBA_NWAYC_FD)

#define	BBA_HALF_10 (BBA_NWAYC_ANE)

#define	BBA_FULL_10 (BBA_NWAYC_FD)

#define	BBA_NWAYS 0x31

#define	BBA_NWAYS_LS10 (1<<0)

#define	BBA_NWAYS_LS100 (1<<1)

#define	BBA_NWAYS_LPNWAY (1<<2)

#define	BBA_NWAYS_ANCLPT (1<<3)

#define	BBA_NWAYS_100TXF (1<<4)

#define	BBA_NWAYS_100TXH (1<<5)

#define	BBA_NWAYS_10TXF (1<<6)

#define	BBA_NWAYS_10TXH (1<<7)

#define	BBA_GCA 0x32 /* GMAC Configuration A Register, RW, 00h */

#define	BBA_GCA_ARXERRB (1<<3) /* ARXERRB, Accept RX packet with error */

#define	BBA_GCA_TXFIFOCNTEN (1<<6) /* TX FIFO cnt enable */

#define	BBA_MISC 0x3d /* MISC Control Register 1, RW, 3ch */

#define	BBA_MISC_BURSTDMA (1<<0)

#define	BBA_MISC_DISLDMA (1<<1)

#define	BBA_TXFIFOCNT 0x3e/0x3f/ /* Transmit FIFO Counter Register */

#define	BBA_WRTXFIFOD 0x48/-0x4b/ /* Write TX FIFO Data Port Register */

#define	BBA_MISC2 0x50 /* MISC Control Register 2, RW, 00h */

#define	BBA_MISC2_HBRLEN0 (1<<0) /* HBRLEN, Host Burst Read Length */

#define	BBA_MISC2_HBRLEN1 (1<<1) /* " */

#define	BBA_MISC2_RUNTSIZE (1<<2) /* " */

#define	BBA_MISC2_DREQBCTRL (1<<3) /* " */

#define	BBA_MISC2_RINTSEL (1<<4) /* " */

#define	BBA_MISC2_ITPSEL (3<<5) /* " */

#define	BBA_MISC2_AUTORCVR (1<<7) /* Auto RX Full Recovery */

#define	BBA_RX_STATUS_BF (1<<0)

#define	BBA_RX_STATUS_CRC (1<<1)

#define	BBA_RX_STATUS_FAE (1<<2)

#define	BBA_RX_STATUS_FO (1<<3)

#define	BBA_RX_STATUS_RW (1<<4)

#define	BBA_RX_STATUS_MF (1<<5)

#define	BBA_RX_STATUS_RF (1<<6)

#define	BBA_RX_STATUS_RERR (1<<7)

#define	BBA_TX_STATUS_CC0 (1<<0)

#define	BBA_TX_STATUS_CC1 (1<<1)

#define	BBA_TX_STATUS_CC2 (1<<2)

#define	BBA_TX_STATUS_CC3 (1<<3)

#define	BBA_TX_STATUS_CCMASK (0x0f)

#define	BBA_TX_STATUS_CRSLOST (1<<4)

#define	BBA_TX_STATUS_UF (1<<5)

#define	BBA_TX_STATUS_OWC (1<<6)

#define	BBA_TX_STATUS_OWN (1<<7)

#define	BBA_TX_STATUS_TERR (1<<7)

#define	BBA_SI_ACTRL 0x5c

#define	BBA_SI_STATUS 0x5d

#define	BBA_SI_ACTRL2 0x60

#define	BBA_INIT_TLBP 0x00

#define	BBA_INIT_BP 0x01

#define	BBA_INIT_RHBP 0x0f

#define	BBA_INIT_RWP BBA_INIT_BP

#define	BBA_INIT_RRP BBA_INIT_BP

#define	BBA_TX_MAX_PACKET_SIZE (1518) /* 14+1500+4 */

#define	BBA_RX_MAX_PACKET_SIZE (1536) /* 6 pages * 256 bytes */

#define	BBA_NAPI_WEIGHT 16

#define	X(a, b) b,a

#define	_SHIFTL(v, s, w) ((u32) (((u32)(v) & ((0x01 << (w)) - 1)) << (s)))

#define	_SHIFTR(v, s, w) ((u32)(((u32)(v) >> (s)) & ((0x01 << (w)) - 1)))

#define	bba_select() EXI_Select(EXI_CHANNEL_0,EXI_DEVICE_2,EXI_SPEED32MHZ)

#define	bba_deselect() EXI_Deselect(EXI_CHANNEL_0)

#define	bba_sync() EXI_Sync(EXI_CHANNEL_0)

#define	bba_in12(reg) ((bba_in8((reg))&0xff)\|((bba_in8(((reg)+1))&0x0f)<<8))

#define	bba_out12(reg, val)

#define	bba_in16(reg) ((bba_in8((reg))&0xff)\|((bba_in8(((reg)+1))&0xff)<<8))

#define	bba_out16(reg, val)

Functions
struct bba_descr	__attribute ((packed))

u32	X (X(next_packet_ptr:12, packet_len:12), status:8)

static err_t	__bba_link_tx (struct netif dev, struct pbuf p)

static u32	__bba_rx_err (u8 status, struct bba_priv *priv)

void	udelay (int us)

static __inline__ void	bba_cmd_insnosel (u32 reg, void *val, u32 len)

static __inline__ void	bba_cmd_outsnosel (u32 reg, void *val, u32 len)

static __inline__ void	bba_insnosel (u32 reg, void *val, u32 len)

static __inline__ void	bba_outsnosel (u32 reg, void *val, u32 len)

static __inline__ void	bba_insregister (u32 reg)

static __inline__ void	bba_insdata (void *val, u32 len)

static __inline__ void	bba_insdmadata (void val, u32 len, s32(dmasubrcv)(s32 chn, s32 dev))

static void	bba_insdata_fast (void *val, s32 len)

static __inline__ void	bba_outsregister (u32 reg)

static __inline__ void	bba_outsdata (void *val, u32 len)

static __inline__ void	bba_outsdmadata (void val, u32 len, s32(dmasubsnd)(s32 chn, s32 dev))

static void	bba_outsdata_fast (void *val, s32 len)

static void	bba_cmd_ins (u32 reg, void *val, u32 len)

static void	bba_cmd_outs (u32 reg, void *val, u32 len)

static u8	bba_cmd_in8 (u32 reg)

static u8	bba_cmd_in8_slow (u32 reg)

static void	bba_cmd_out8 (u32 reg, u8 val)

static void	bba_ins (u32 reg, void *val, u32 len)

static void	bba_outs (u32 reg, void *val, u32 len)

static u8	bba_in8 (u32 reg)

static void	bba_out8 (u32 reg, u8 val)

static s32	__bba_exi_unlockcb (s32 chn, s32 dev)

static __inline__ void	__bba_exi_stop (struct bba_priv *priv)

static __inline__ void	__bba_exi_wake (struct bba_priv *priv)

static __inline__ void	__bba_tx_stop (struct bba_priv *priv)

static __inline__ void	__bba_tx_wake (struct bba_priv *priv)

static __inline__ u8	__linkstate (struct bba_priv *priv)

static bool	__bba_get_linkstateasync (struct bba_priv *priv)

static u32	__bba_read_cid ()

static void	__bba_reset ()

static void	__bba_recv_init ()

static u32	__bba_tx_err (u8 status, struct bba_priv *priv)

void	bba_process (struct pbuf p, struct netif dev)

static err_t	__bba_start_tx (struct netif dev, struct pbuf p, struct ip_addr *ipaddr)

static err_t	bba_start_rx (struct netif *dev, u32 budget)

static void	bba_interrupt (struct netif *dev)

static err_t	__bba_init (struct netif *dev)

static err_t	bba_init_one (struct netif *dev)

static err_t	bba_probe (struct netif *dev)

static u32	bba_calc_response (struct bba_priv *priv, u32 val)

static s32	bba_event_handler (s32 nChn, s32 nDev)

err_t	bba_init (struct netif *dev)

dev_s	bba_create (struct netif *dev)

Variables
struct bba_priv	__attribute

static lwpq_t	wait_exi_queue

static struct bba_descr	cur_descr

static struct netif *	gc_netif = NULL

static const struct eth_addr	ethbroadcast = {{0xffU,0xffU,0xffU,0xffU,0xffU,0xffU}}

Macro Definition Documentation

◆ _SHIFTL

#define _SHIFTL	(	v,
		s,
		w
	)	((u32) (((u32)(v) & ((0x01 << (w)) - 1)) << (s)))

◆ _SHIFTR

#define _SHIFTR	(	v,
		s,
		w
	)	((u32)(((u32)(v) >> (s)) & ((0x01 << (w)) - 1)))

◆ BBA_BP

#define BBA_BP 0x0a/*+0x0b*/ /* Boundary Page Pointer Register */

◆ BBA_CID

#define BBA_CID 0x04020200

◆ BBA_CMD_IRMASKALL

#define BBA_CMD_IRMASKALL 0x00

◆ BBA_CMD_IRMASKNONE

#define BBA_CMD_IRMASKNONE 0xF8

◆ bba_deselect

#define bba_deselect ( ) EXI_Deselect(EXI_CHANNEL_0)

◆ BBA_FULL_10

#define BBA_FULL_10 (BBA_NWAYC_FD)

◆ BBA_FULL_100

#define BBA_FULL_100 (BBA_NWAYC_PS100|BBA_NWAYC_FD)

◆ BBA_GCA

#define BBA_GCA 0x32 /* GMAC Configuration A Register, RW, 00h */

◆ BBA_GCA_ARXERRB

#define BBA_GCA_ARXERRB (1<<3) /* ARXERRB, Accept RX packet with error */

◆ BBA_GCA_TXFIFOCNTEN

#define BBA_GCA_TXFIFOCNTEN (1<<6) /* TX FIFO cnt enable */

◆ BBA_HALF_10

#define BBA_HALF_10 (BBA_NWAYC_ANE)

◆ BBA_HALF_100

#define BBA_HALF_100 (BBA_NWAYC_PS100)

◆ BBA_IMR

#define BBA_IMR 0x08 /* Interrupt Mask Register, RW, 00h */

◆ BBA_IMR_BUSEIM

#define BBA_IMR_BUSEIM (1<<6) /* BUSEIM, BUS Error Interrupt Mask */

◆ BBA_IMR_FIFOEIM

#define BBA_IMR_FIFOEIM (1<<5) /* FIFOEIM, FIFO Error Interrupt Mask */

◆ BBA_IMR_FRAGIM

#define BBA_IMR_FRAGIM (1<<0) /* FRAGIM, Fragment Counter Int Mask */

◆ BBA_IMR_RBFIM

#define BBA_IMR_RBFIM (1<<7) /* RBFIM, RX Buffer Full Interrupt Mask */

◆ BBA_IMR_REIM

#define BBA_IMR_REIM (1<<3) /* REIM, Receive Error Interrupt Mask */

◆ BBA_IMR_RIM

#define BBA_IMR_RIM (1<<1) /* RIM, Receive Interrupt Mask */

◆ BBA_IMR_TEIM

#define BBA_IMR_TEIM (1<<4) /* TEIM, Transmit Error Interrupt Mask */

◆ BBA_IMR_TIM

#define BBA_IMR_TIM (1<<2) /* TIM, Transmit Interrupt Mask */

◆ bba_in12

#define bba_in12 ( reg ) ((bba_in8((reg))&0xff)|((bba_in8(((reg)+1))&0x0f)<<8))

◆ bba_in16

#define bba_in16 ( reg ) ((bba_in8((reg))&0xff)|((bba_in8(((reg)+1))&0xff)<<8))

◆ BBA_INIT_BP

#define BBA_INIT_BP 0x01

◆ BBA_INIT_RHBP

#define BBA_INIT_RHBP 0x0f

◆ BBA_INIT_RRP

#define BBA_INIT_RRP BBA_INIT_BP

◆ BBA_INIT_RWP

#define BBA_INIT_RWP BBA_INIT_BP

◆ BBA_INIT_TLBP

#define BBA_INIT_TLBP 0x00

◆ BBA_IR

#define BBA_IR 0x09 /* Interrupt Register, RW, 00h */

◆ BBA_IR_BUSEI

#define BBA_IR_BUSEI (1<<6) /* BUSEI, BUS Error Interrupt */

◆ BBA_IR_FIFOEI

#define BBA_IR_FIFOEI (1<<5) /* FIFOEI, FIFO Error Interrupt */

◆ BBA_IR_FRAGI

#define BBA_IR_FRAGI (1<<0) /* FRAGI, Fragment Counter Interrupt */

◆ BBA_IR_RBFI

#define BBA_IR_RBFI (1<<7) /* RBFI, RX Buffer Full Interrupt */

◆ BBA_IR_REI

#define BBA_IR_REI (1<<3) /* REI, Receive Error Interrupt */

◆ BBA_IR_RI

#define BBA_IR_RI (1<<1) /* RI, Receive Interrupt */

◆ BBA_IR_TEI

#define BBA_IR_TEI (1<<4) /* TEI, Transmit Error Interrupt */

◆ BBA_IR_TI

#define BBA_IR_TI (1<<2) /* TI, Transmit Interrupt */

◆ BBA_LRPS

#define BBA_LRPS 0x05 /* Last Received Packet Status, RO */

◆ BBA_LTPS

#define BBA_LTPS 0x04 /* Last Transmitted Packet Status, RO */

◆ BBA_MINPKTSIZE

#define BBA_MINPKTSIZE 60

◆ BBA_MISC

#define BBA_MISC 0x3d /* MISC Control Register 1, RW, 3ch */

◆ BBA_MISC2

#define BBA_MISC2 0x50 /* MISC Control Register 2, RW, 00h */

◆ BBA_MISC2_AUTORCVR

#define BBA_MISC2_AUTORCVR (1<<7) /* Auto RX Full Recovery */

◆ BBA_MISC2_DREQBCTRL

#define BBA_MISC2_DREQBCTRL (1<<3) /* " */

◆ BBA_MISC2_HBRLEN0

#define BBA_MISC2_HBRLEN0 (1<<0) /* HBRLEN, Host Burst Read Length */

◆ BBA_MISC2_HBRLEN1

#define BBA_MISC2_HBRLEN1 (1<<1) /* " */

◆ BBA_MISC2_ITPSEL

#define BBA_MISC2_ITPSEL (3<<5) /* " */

◆ BBA_MISC2_RINTSEL

#define BBA_MISC2_RINTSEL (1<<4) /* " */

◆ BBA_MISC2_RUNTSIZE

#define BBA_MISC2_RUNTSIZE (1<<2) /* " */

◆ BBA_MISC_BURSTDMA

#define BBA_MISC_BURSTDMA (1<<0)

◆ BBA_MISC_DISLDMA

#define BBA_MISC_DISLDMA (1<<1)

◆ BBA_NAFR_PAR0

#define BBA_NAFR_PAR0 0x20 /* Physical Address Register Byte 0 */

◆ BBA_NAFR_PAR1

#define BBA_NAFR_PAR1 0x21 /* Physical Address Register Byte 1 */

◆ BBA_NAFR_PAR2

#define BBA_NAFR_PAR2 0x22 /* Physical Address Register Byte 2 */

◆ BBA_NAFR_PAR3

#define BBA_NAFR_PAR3 0x23 /* Physical Address Register Byte 3 */

◆ BBA_NAFR_PAR4

#define BBA_NAFR_PAR4 0x24 /* Physical Address Register Byte 4 */

◆ BBA_NAFR_PAR5

#define BBA_NAFR_PAR5 0x25 /* Physical Address Register Byte 5 */

◆ BBA_NAPI_WEIGHT

#define BBA_NAPI_WEIGHT 16

◆ BBA_NCRA

#define BBA_NCRA 0x00 /* Network Control Register A, RW */

◆ BBA_NCRA_RESET

#define BBA_NCRA_RESET (1<<0) /* RESET */

◆ BBA_NCRA_SR

#define BBA_NCRA_SR (1<<3) /* SR, Start Receive */

◆ BBA_NCRA_ST0

#define BBA_NCRA_ST0 (1<<1) /* ST0, Start transmit command/status */

◆ BBA_NCRA_ST1

#define BBA_NCRA_ST1 (1<<2) /* ST1, " */

◆ BBA_NCRB

#define BBA_NCRB 0x01 /* Network Control Register B, RW */

◆ BBA_NCRB_1_PACKET_PER_INT

#define BBA_NCRB_1_PACKET_PER_INT (0<<6) /* 0 0 */

◆ BBA_NCRB_2_PACKETS_PER_INT

#define BBA_NCRB_2_PACKETS_PER_INT (1<<6) /* 0 1 */

◆ BBA_NCRB_4_PACKETS_PER_INT

#define BBA_NCRB_4_PACKETS_PER_INT (2<<6) /* 1 0 */

◆ BBA_NCRB_8_PACKETS_PER_INT

#define BBA_NCRB_8_PACKETS_PER_INT (3<<6) /* 1 1 */

◆ BBA_NCRB_AB

#define BBA_NCRB_AB (1<<4) /* AB, Accept Broadcast */

◆ BBA_NCRB_CA

#define BBA_NCRB_CA (1<<1) /* CA, Capture Effect Mode */

◆ BBA_NCRB_HBD

#define BBA_NCRB_HBD (1<<5) /* HBD, reserved */

◆ BBA_NCRB_PB

#define BBA_NCRB_PB (1<<3) /* PB, Pass Bad Frame */

◆ BBA_NCRB_PM

#define BBA_NCRB_PM (1<<2) /* PM, Pass Multicast */

◆ BBA_NCRB_PR

#define BBA_NCRB_PR (1<<0) /* PR, Promiscuous Mode */

◆ BBA_NCRB_RXINTC0

#define BBA_NCRB_RXINTC0 (1<<6) /* RXINTC, Receive Interrupt Counter */

◆ BBA_NCRB_RXINTC1

#define BBA_NCRB_RXINTC1 (1<<7) /* " */

◆ BBA_NWAYC

#define BBA_NWAYC 0x30 /* NWAY Configuration Register, RW, 84h */

◆ BBA_NWAYC_ANE

#define BBA_NWAYC_ANE (1<<2) /* ANE, Autonegotiation Enable */

◆ BBA_NWAYC_ANS_RA

#define BBA_NWAYC_ANS_RA (1<<3) /* ANS, Restart Autonegotiation */

◆ BBA_NWAYC_FD

#define BBA_NWAYC_FD (1<<0) /* FD, Full Duplex Mode */

◆ BBA_NWAYC_LTE

#define BBA_NWAYC_LTE (1<<7) /* LTE, Link Test Enable */

◆ BBA_NWAYC_PS100

#define BBA_NWAYC_PS100 (1<<1) /* PS100/10, Port Select 100/10 */

◆ BBA_NWAYS

#define BBA_NWAYS 0x31

◆ BBA_NWAYS_100TXF

#define BBA_NWAYS_100TXF (1<<4)

◆ BBA_NWAYS_100TXH

#define BBA_NWAYS_100TXH (1<<5)

◆ BBA_NWAYS_10TXF

#define BBA_NWAYS_10TXF (1<<6)

◆ BBA_NWAYS_10TXH

#define BBA_NWAYS_10TXH (1<<7)

◆ BBA_NWAYS_ANCLPT

#define BBA_NWAYS_ANCLPT (1<<3)

◆ BBA_NWAYS_LPNWAY

#define BBA_NWAYS_LPNWAY (1<<2)

◆ BBA_NWAYS_LS10

#define BBA_NWAYS_LS10 (1<<0)

◆ BBA_NWAYS_LS100

#define BBA_NWAYS_LS100 (1<<1)

◆ bba_out12

#define bba_out12	(	reg,
		val
	)

Value:

do { \
 bba_out8((reg),((val)&0xff)); \
 bba_out8(((reg)+1),(((val)&0x0f00)>>8)); \
 } while(0)

◆ bba_out16

#define bba_out16	(	reg,
		val
	)

Value:

do { \
 bba_out8((reg),((val)&0xff)); \
 bba_out8(((reg)+1),(((val)&0xff00)>>8)); \
 } while(0)

◆ BBA_RHBP

#define BBA_RHBP 0x1a/*+0x1b*/ /* Receive High Boundary Page Pointer Register */

◆ BBA_RRP

#define BBA_RRP 0x18/*+0x19*/ /* Receive Buffer Read Page Pointer Register */

◆ BBA_RWP

#define BBA_RWP 0x16/*+0x17*/ /* Receive Buffer Write Page Pointer Register */

◆ BBA_RX_MAX_PACKET_SIZE

#define BBA_RX_MAX_PACKET_SIZE (1536) /* 6 pages * 256 bytes */

◆ BBA_RX_STATUS_BF

#define BBA_RX_STATUS_BF (1<<0)

◆ BBA_RX_STATUS_CRC

#define BBA_RX_STATUS_CRC (1<<1)

◆ BBA_RX_STATUS_FAE

#define BBA_RX_STATUS_FAE (1<<2)

◆ BBA_RX_STATUS_FO

#define BBA_RX_STATUS_FO (1<<3)

◆ BBA_RX_STATUS_MF

#define BBA_RX_STATUS_MF (1<<5)

◆ BBA_RX_STATUS_RERR

#define BBA_RX_STATUS_RERR (1<<7)

◆ BBA_RX_STATUS_RF

#define BBA_RX_STATUS_RF (1<<6)

◆ BBA_RX_STATUS_RW

#define BBA_RX_STATUS_RW (1<<4)

◆ BBA_RXINTT

#define BBA_RXINTT 0x14/*+0x15*/ /* Receive Interrupt Timer Register */

◆ bba_select

#define bba_select ( ) EXI_Select(EXI_CHANNEL_0,EXI_DEVICE_2,EXI_SPEED32MHZ)

◆ BBA_SI_ACTRL

#define BBA_SI_ACTRL 0x5c

◆ BBA_SI_ACTRL2

#define BBA_SI_ACTRL2 0x60

◆ BBA_SI_STATUS

#define BBA_SI_STATUS 0x5d

◆ bba_sync

#define bba_sync ( ) EXI_Sync(EXI_CHANNEL_0)

◆ BBA_TLBP

#define BBA_TLBP 0x0c/*+0x0d*/ /* TX Low Boundary Page Pointer Register */

◆ BBA_TRP

#define BBA_TRP 0x12/*+0x13*/ /* Transmit Buffer Read Page Pointer Register */

◆ BBA_TWP

#define BBA_TWP 0x0e/*+0x0f*/ /* Transmit Buffer Write Page Pointer Register */

◆ BBA_TX_MAX_PACKET_SIZE

#define BBA_TX_MAX_PACKET_SIZE (1518) /* 14+1500+4 */

◆ BBA_TX_STATUS_CC0

#define BBA_TX_STATUS_CC0 (1<<0)

◆ BBA_TX_STATUS_CC1

#define BBA_TX_STATUS_CC1 (1<<1)

◆ BBA_TX_STATUS_CC2

#define BBA_TX_STATUS_CC2 (1<<2)

◆ BBA_TX_STATUS_CC3

#define BBA_TX_STATUS_CC3 (1<<3)

◆ BBA_TX_STATUS_CCMASK

#define BBA_TX_STATUS_CCMASK (0x0f)

◆ BBA_TX_STATUS_CRSLOST

#define BBA_TX_STATUS_CRSLOST (1<<4)

◆ BBA_TX_STATUS_OWC

#define BBA_TX_STATUS_OWC (1<<6)

◆ BBA_TX_STATUS_OWN

#define BBA_TX_STATUS_OWN (1<<7)

◆ BBA_TX_STATUS_TERR

#define BBA_TX_STATUS_TERR (1<<7)

◆ BBA_TX_STATUS_UF

#define BBA_TX_STATUS_UF (1<<5)

◆ BBA_TXFIFOCNT

#define BBA_TXFIFOCNT 0x3e/*0x3f*/ /* Transmit FIFO Counter Register */

◆ BBA_WRTXFIFOD

#define BBA_WRTXFIFOD 0x48/*-0x4b*/ /* Write TX FIFO Data Port Register */

◆ GCIF_EXI_TQ

#define GCIF_EXI_TQ 9

◆ GCIF_TX_TQ

#define GCIF_TX_TQ 8

◆ IFNAME0

#define IFNAME0 'e'

◆ IFNAME1

#define IFNAME1 '0'

◆ X

#define X	(	a,
		b
	)	b,a

Function Documentation

◆ __attribute()

struct bba_descr __attribute ( (packed) )